Why should we care about RTL signoff?
1 October, 2013
If your next design project is targeting 28nm or below, is more than a couple hundred million gates, and includes more than 10 IP blocks, then you probably already care.
By Piyush Sancheti, Vice President, Product Marketing Atrenta Inc.
After all, using early signoff (i.e., RTL signoff) to supplement post-layout signoff is like finding design mistakes in your architect’s blueprints rather than finding them on the job site…and then having to tear them out. You save a lot of time, money and materials. In the case of SoCs, you could save anywhere from 30 to 50% of your overall design schedule.
“RTL signoff” is not a new term, but has become fashionable in 2013. But just what does the term mean? After all, RTL signoff has been discussed for a long time, maybe twenty years or more. The history is real, but the reality of what’s possible, and what’s useful, has evolved. Today, RTL signoff means a series of well-defined MUST-pass requirements that your design needs to achieve before moving to the next phase in the design flow. That next phase is often synthesis, place & route.
RTL signoff spans both design and verification. The goal? You’re ability to say, “I cleared this requirement and so I don’t have to worry about these issues.” Obviously, the more requirements you check, the better.
There are two SoC challenges that mandate RTL signoff…
- The increasing complexity of SoC design that complicates chip assembly and validation
- The varied quality of third party IP that impedes the quality assurance process
Running checks at RTL will detect a lot of these problems. The result? Post-layout signoff will have an easier job sending the design to tapeout. Why is RTL signoff such a good idea? At least two points to note…
- Runtimes at RTL are an order of magnitude less than runtimes in post-layout. If your RTL tools have good quality of results, you can simply find and fix a lot more problems per unit of time
- Errors caught at the post-layout phase have to go back through the complete design flow, an arduous and time-killing consequence, especially if your customer is waiting for your SoC to go into the Christmas season-targeted consumer product
I want to emphasize an important point: both signoff processes are needed, even though some experts have claimed that RTL signoff obviates the need for post-layout signoff.
But, as with all things, there are different shades and grades of RTL signoff. In my mind, checking off a comprehensive set of MUST-pass requirements is imperative to optimal post-layout signoff and, ultimately, an on-schedule tapeout.
These MUST-pass requirements include:
- Functional coverage (including high quality assertions)
- Clock domain crossings (static and dynamic verification)
- Timing constraints (including false and multi-cycle paths)
- Power consumption (and meeting the power budget)
- Power intent (CPF/UPF correct?)
- Testability (stuck-at and at-speed coverage OK?)
- Routability (congestion OK; area and timing OK?)
There are other schools of thought, RE: what constitutes reliable RTL signoff. Running SoC designs through rigorous checks of a few to several critical functions certainly saves time and focuses RTL signoff resources on where your SoC might most likely have problems.
But that’s a lot like saying a car doesn’t need a chassis and four wheels to roll…that you only need three wheels and the car more than likely will roll fine. It’s a decent bet…but I also bet that a lot of SoC designers would prefer to have the chassis and four wheels approach and be absolutely sure their SoC has signed off at RTL.
Integral part of design flow
So the upshot is that SoC design teams are already starting to think about RTL signoff as an integral part of their design flow. And those that have started thinking about it need to start defining the specifics of RTL signoff, based on how safe they want their design to be before it gets to post-layout signoff.
In my mind, the more comprehensively RTL signoff is defined, the more likely your SoC will be able to tape out on time and in budget after post-layout signoff. As more and more SoC designs are targeting 14nm geometries and including more and more third party IP, everyone should come to this same conclusion.
Published at Chip Design