Atrenta has found a surprising market in Israel
27 July, 2014
Atrenta Vice President of Marketing Sancheti: "We discovered a way to make RTL Signoff during the Front-end phase"
Atrenta Vice President of Marketing Sancheti: “We discovered a way to make RTL Signoff during the Front-end phase”
The third annual Atrenta seminar, held about three weeks ago in Herzliya near Tel-aviv, was attended by some of Israel’s major chip designers, some of whom are world leaders in the field. According to Mr Piyush Sancheti, Atrenta Vice President of Marketing of the American company, this is still a surprising discovery.
“When we arrived in Israel we were surprised by the immense talent here. We previously did not consider Israel to be an important market. However when we began to get to know the market we were surprised to discover that the people here have a huge influence on the behavior of major global companies. Maybe this is due to Israel’s aggressively-innovative culture. Today all international R&D centers in Israel are our customers.”
Workflow Changes in Chip Design
The seminar was dedicated to introducing RTL Signoff, a key developing area in chip design. Signoff is an integral concept and extremely important in all the levels of a chips design and production. Basically, this is the verification stage performed at the end of each development or production phase of the chip, aimed to confirm that the chip is ready for the next step of the process.
Chip manufacturers demand that all design files given to them undergo signoff assurance to ensure design integrity before starting the long and expensive production procedure. Principally, the production of new chips is based on two main phases: Front-end and Back-end. Design starts at the front-end stage, where the designers define the chip in RTL language.
RTL, a hardware description language, describes the general behavior of the chip. This information is then translated to a physical level known as the Back-end phase, which defines the gates and the connections between. Most large EDA software companies, for example, Cadence, Synphosys, Mentor Graphics and others, concentrate on this phase.
Atrenta discovered a way to perform a Signoff process during the RTL phase. That is, verify design and identify problems such as timing before they become an issue later on during the Back-end phase. The advantage is clear: Early detection at the RTL phase enables fixing mistakes before investing time and money in design. Making repairs is quicker and easier at RTL level and ensures that Back-end engineers receive clean and quality code for chip design.
Sancheti: “Testing during Back-end stages is no longer effective. Today’s designs are more complex, include hundreds of millions of gates and multiple IP modules from many external sources. This is the reason the RTL Signoff is growing quickly. It saves a lot of Back-end work, which is the most expensive and intensive part of chip design”.
What are your relationships with the big EDA providers?
“We hold a neutral position regarding competition between them. Our solution does not depend on whether the customer uses tools from Cadence or Synopsys. In reality, both Cadence and Synopsys use our tools for their IP business development.”
25% Annual growth
Atrenta operates from San Jose, California, and have 350 employees in five R&D centers in India, France, China, Sri Lanka and the USA. Last year their sales reached $50 Million. The company expect to reach approximately 25% growth during 2014, following 20% growth in 2013.
VP for Formal Verification at Atrenta, Mr Shaker Sarwery, explained that the formal verification process examines the internal logic of the design to confirm that features have not been excluded or that functions do not compete or clash with each other.
“Time management inside a chip, for example, is one of the major problems in SoC design today. We are talking about chips with hundreds of internal clocks which require synchronization to thousands of interfaces. Our CDC SpyGlass product can confirm synchronization between all asynchronous clocks of the entire SoC. In reality the larger the chips become, the more our sales grow”.
During the seminar in Herzliya, the company disclosed a chip design project with 1.4 Billion gates which took SpyGlass only one night to run.
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