TowerJazz Announced a 65nm BCD Power Platform
2 May, 2018
The new process combines Analog components, Digital components and high-voltage transistors on the same die. TowerJazz addresses the growing Power Management market
TowerJazz announced the release of a new process for power management devices, perfected from its existing automotive process knowhow. The new 300mm 65nm BCD (Bipolar-CMOS-DMOS) process provides power management platform for up to 16V operation and 24V maximum voltage. This technology is manufactured in TowerJazz’s Uozu, Japan facility, and is based on the Company’s 300mm 65nm automotive qualified flows.
BCD technology is a process that emerged during the last decade and is dedicated for products that receive Analog input, Digital controlling signals and produce Power output to activate external circuits or devices. It is typically incorporates analog components (Bipolar), digital components (CMOS) and high-voltage transistors (DMOS) on the same semiconductor die (photo above). It reduces the number of components in the bill of materials (BoM), the total cost and helps reduce the parasitic losses.
The new Towerjazz’ platform addresses the markets of power management chips up to 16V, including products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson, forecasts a $9.4 billion total available market for BCD process in 2018, with continual growth prospects.
TowerJazz’s 65nm BCD process includes four high performance power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip modules. The power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, less than 1mΩ*mm² for the 5V LDMOS.
For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors provides low Qgd down to 2.6mΩ*nC. It HAS very low metal resistance is achieved using a single or dual 3.3um top thick copper. The process offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.