Applied Materials Introduced Cobalt for Chip Interconnects
6 June, 2018
"This is first metal change to transistor contact and interconnect in 20 years. It removes major performance bottleneck at the 7nm foundry node and beyond"
Applied Materials, Inc. today announced a breakthrough in materials engineering that accelerates chip performance by up to 15%. The company said this is first metal change to transistor contact and interconnect in 20 years after the introduction of copper. “It removes major performance bottleneck at the 7nm foundry node and beyond. Materials such as tungsten and copper are no longer scalable beyond the 10nm foundry node because their electrical performance has reached physical limits for transistor contacts and local interconnects.”
This has created a major bottleneck in achieving the full performance potential of FinFET transistors. “Five years ago, Applied anticipated an inflection in the transistor contact and interconnect, and we began developing an alternative materials solution that could take us beyond the 10nm node,” said Dr. Prabu Raja, senior vice president of Applied’s Semiconductor Products Group. For the 7nm node and beyond, the increasing resistance in tungsten gapfill results in higher power consumption and slower chip performance.
First-level copper interconnects face similar challenges as resistance rises with decreasing copper volume, also slowing chip performance. Cobalt also demonstrates better line and via resistance scaling and less electromigration than copper, facilitating higher current densities. Cobalt is about to remove this bottleneck, but it requires a change in process system strategy. The company combined three new deposition processes are complemented by a new anneal product and a production-proven CMP tool to comprise an end-to-end process suite that makes it possible to use cobalt as a conducting material.
It includes: Applied Endura Cirrus RT PVD Cobalt To deposit the initial thin layer of cobalt to which the subsequent CVD cobalt adheres. Applied Endura Volta CVD Co to deposit the cobalt fill following the PVD layer. The seam created by this deposition process is subsequently eliminated during the anneal step. Applied Endura Versa XT PVD Co to deposit the thick overburden following the anneal step. Applied Producer Pyra Anneal to heats the wafer, causing cobalt reflow that eliminates the seam in the bulk fill, enlarges the grain size, purifies the cobalt, and reduces the resistance. Applied Reflexion LK Prime CMP: Using slurries specifically optimized for polishing cobalt, this system removes the overburden produced by earlier deposition steps and creates a planar surface for subsequent process steps.
Applied’s integrated cobalt suite is now shipping to foundry/logic customers worldwide.
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