Amir Faintuch to lead CWI Unit of Globalfoundries

4 November, 2019

The appointment is part of GLOBALFOUNDRIES' reorganization that includes the establishment of dedicated strategic business units around three core market groups

As part of its new vertical reorganization, GLOBALFOUNDRIES appointed Amir Faintuch as senior vice president and general manager of the computing and wired infrastructure (CWI) business unit (SBU). Faintuch will oversee the strategic direction, roadmap definition and client engagements.

GLOBALFOUNDRIES’ reorganization includes the establishment of dedicated strategic business units around three core market groups: Automotive, Industrial and Multi-market (AIM); Mobile and Wireless Infrastructure (MWI); and Computing and Wired Infrastructure (CWI).  GLOBALFOUNDRIES  is considered the second largest provider of Semiconductor production services, following the leader TSMC. It plan to expand its presence in the $47 billion addressable foundry market for 12nm technologies and above.

Faintuch  brings to the job more than 25 years of experience in the semiconductor, communications and software industries. Prior to joining GF, he had served for four years as Senior Vice President & General Manager of Intel’s Platform Engineering Group (PEG). He was brought to Intel from its fierce competitor Qualcomm, where he held the position of President of Qualcomm Atheros, a subsidiary of Qualcomm Inc. that develops networking, connectivity infrastructure and Internet of Things components.

New Platform for AI chips

 “The growing demand for AI technology and high performance compute solutions represent a significant opportunity,” said Thomas Caulfield, CEO of GF. “As GF continues to build its specialized application solutions to meet our clients’ needs, Amir’s expertise will help further advance our strategic cloud and client offerings.” The appointment comes on the heels of recent GF announcements regarding the availability of 12LP+, GF’s new innovative solution for AI training and inference applications.

Derived from GF’s existing 12nm (12LP) platform, the new 12LP+ provides either a 20% increase in performance or a 40% reduction in power requirements over the base 12LP platform, plus a 15% improvement in logic area scaling. A key feature is a high-speed, low-power 0.5V SRAM bit cell that supports the fast, power-efficient shuttling of data between processors and memory, an important requirement for AI applications.

 Another key feature of 12LP+ is a new interposer for 2.5D packages, which facilitates the integration of high-bandwidth memory with processors. According to Michael Mendicino, vice president of Digital Technology Solutions at GF, “12LP+ solution offers clients the performance and power advantages they would expect to gain from a 7nm process, but with half the costs.” The 12LP+ PDK is available now and GF is already working with several clients. Tape outs are expected in the second half of 2020 and volume production is set for 2021 from GF’s Fab 8 in Malta, New York.

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