CEVA added Floating point to multicore DSP platform

19 February, 2013

The new MUST suite answers the needs of LTE MIMO. Linley Group: "It offer SoC designers a comprehensive environment to develop high-speed data flow in multi-core designs".

The new MUST suite answers the needs of LTE MIMO

ceva_mustCEVA announced a suite of advanced  processor and multi-core technologies under the code name MUST (Multi-core System Technology), that enhance its CEVA-XC DSP architecture framework. Among the new enhancements are: comprehensive multi-core features, high-throughput vector floating-point processing and a complete set of co-processor engines offering power-efficient hardware-software partitioning. CEVA has collaborated closely with leading OEMs, wireless semiconductors and IP partners for the definition and optimization of these technologies.

J. Scott Gardner, Senior Analyst at The Linley Group, commented: “The new enhancements offer SoC designers a comprehensive environment to develop high-speed data flow in multi-core designs. The use of ARM’s latest interconnect and coherency protocols, together with advanced automated data traffic managers, as well as a dynamic scheduling software framework, position CEVA as the only DSP licensor today offering such extensive support for multi-core DSP-based SoCs. When combined with vectorized floating-point support and a wide range of coprocessor engines, the CEVA-XC architecture framework includes all the essential DSP platform components for a wide range of user equipment and infrastructure applications.”

Aadvanced multi-core system technology

CEVA-XCCEVA’s MUST™ is a cache-based multi-core system technology with advanced support for cache coherency, resource sharing and data management. CEVA has also added extensive support for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions. This simplifies the software development and debugging process for SoC designs, while also reducing the software cache management overhead, processor cycles and external memory bandwidth.

The LTE-Advanced and 802.11ac standards leverage multiple input multiple output (MIMO) processing, where the system utilizes multiple antennae to transmit and receive data. In order to achieve ultra-high precision and optimal performance when processing these complex data streams, CEVA has added support for floating-point operations to the CEVA-XC vector processor unit, in addition to the traditional fixed-point capabilities. Floating-point operations are supported on full vector elements, processing up to 32 floating point operations in every core cycle.

In addition to these enhancements, CEVA has supplied a dedicated instruction set architecture (ISA) for high-dimension MIMO, including support for 802.11ac 4×4 use cases, and a tightly-coupled extension coprocessorsthat address functions of the modem where greater performance can be achieved through the use of hardware.

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