Software Designers get 9 Months Head Start before a new Chip is “Born”
5 January, 2014
Dr. Johannes Stahl, Director of Product Marketing for the Virtual Prototyping Division at Synopsys: "When a new chip is launched, it is necessary to have fully integrated and validated software to run the chip, otherwise it is useless."
Dr. Johannes Stahl of Synopsys: “Altera have delivered a virtual prototype of the new SoC FPGA, about 12 months before the physical silicon went for production”
Modern chip design complexities turn the traditional design workflow model upside down.
With millions of lines of software code needed to run the new billion-transistors, SoCs, OEMs and semiconductor companies can’t wait until physical semiconductor devices leaving the production floor to begin the software code design.
Semiconductors upside down
They must start the programming of the final products months before the hardware becomes available to them. According to Dr. Johannes Stahl, Director of Product Marketing for the Virtual Prototyping Division at Synopsys Inc., “they need at least nine to twelve months head start before the first silicon is available from production”, in order to meet the strict time to market demand.
“When a new chip is launched, it is necessary to have fully integrated and validated software to run the chip, otherwise it is useless.” Sometime even longer: “When Altera began to work on its ARM-based dual core FPGA, they delivered their customers a virtual prototype of the new SoC FPGA, about 12 months before the physical silicon went for production.”
Dr. Stahl is responsible for all software development, architecture design, and algorithm design tools at Synopsys. He explained that this shift has led Synopsys during 2011 to introduce its Virtualizer™ tool for virtual prototype developers and virtual prototype users. Virtualizer enables the early creation of SystemC-based transaction-level models (the modeling language SystemC was developed by Synopsys and its partners during the 90’s) of subsystems, and the assembly of those TLMs into virtual prototypes representing the complete system.
Software Representation of the Silicon
The Virtualizer tool set enables the creation of basic modeling blocks and the assembly of these blocks into a virtual prototype of the SoC or system. And, for the end users of virtual prototypes it provide the tools and interfaces for use cases such as software development and test, or system validation/testing.
What are your latest upgrades for Virtualizer?
Dr. Johannes Stahl: “We continue to increase our support for software engineers and give more capabilities to virtual prototype developers. For example, we upgraded the connectivity between Virtualizer and the open source Eclipse Debugger. This is very important for software engineers since they are familiar and used to working in the Eclipse environment.”
How does Synopsys position Virtualizer for the different processors inside SoC chips?
“It is clear that vertical markets demand different models to address the needs of different specific functions. We created TLM models of various platforms, like ARM, Freescale, Renesas and Infineon. Designers can find the industry repository of TLM models ready for use in the TLM Central portal (www.tlmcentral.com), which is now hosted by Design & Reuse. It includes the IP models of processor cores and virtual platforms needed to quickly assemble new virtual prototypes.”
What can you tell about the Israeli market?
“In Israel we work mainly with the multi-national development centers, but we also have customers among local smaller firms. For example, we just recently announced the success of a collaborative effort with CEVA to develop highly optimized DSP core implementations for wireless communications applications, including base stations and handsets.
“The project was done using Synopsys DesignWare HPC Design Kit, a processor optimization kit, in order to optimize CEVA-XC DSP cores. CEVA achieved 8% performance improvement, 10% less power and a maximum performance of 1.3 GHz in a 28-nm process.”
Synopsys, Inc. is a leading EDA and IP provider in the global market. During the fourth quarter of 2013, the company reported revenue of $504.9 million, compared to $454.2 million in Q4 2012. Revenue for fiscal year 2013 was $1.962 billion, an increase of 11.7% compared to fiscal year 2012.