2D Materials-Based FETs for High Performance Logic

16 July, 2017

Using the material monolayer black-phosphorus, imec's researchers presented novel device designs that pave the way into sub-5nm gate length

Imec Semiconductors Technology

imec, the semiconductor’s research hub, announced in At its annual Imec Technology Forum USA in San Francisco, that its researchers, in collaboration with scientists from KU Leuven in Belgium and Pisa University, Italy, have performed the first material-device-circuit level co-optimization of field-effect transistors (FETs) based on 2D materials for high-performance logic applications. Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5nm gate length.

2D materials is a family of materials that form two-dimensional crystals, that may be used to create the new kinds of transistor with a channel thickness down to the level of single atoms and gate length of few nanometers. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to vertical FinFETs. They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks even further, and is replacing the transistor channel material, with 2D materials as some of the prime candidates.

In order to fit FETs based on 2D materials into the scaling roadmap, it is essential to understand how their characteristics relate to their behavior in digital circuits. In the paper published in Scientific Reports paper, the imec scientists and their colleagues presented guidelines on how to choose materials, design the devices and optimize performance to get the circuits that meet the requirements for sub-10nm high-performance logic chips.

imec demonstration of 2D Materials-Based Field-Effect Transistor
imec demonstration of 2D Materials-Based Field-Effect Transistor

Using the material monolayer black-phosphorus, the researchers presented novel device designs that pave the way into sub-5nm gate length. These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling.  These results are very encouraging, because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.

“2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations,” said Iuliana Radu, distinguished member of technical staff at imec. “Our latest results presented in Scientific Reports, show how 2D materials could be used to scale FETs for very advanced technology nodes.”

These results were published in Scientific Reports: T. Agarwal, G. Fiori, B. Soree, I. Radu, P. Raghavan, G. Iannaccone, W. Dehaene, M. Heyns – Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes (SREP-16-50433) www.nature.com/articles/s41598-017-04055-3

This work was supported by imec’s industrial affiliation programs on core CMOS including key partners GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC, and by the European GRAPHENE FLAGSHIP core 1.

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