Marvell, through its R&D center in Israel, lately completed the development of its new DPU processor, OCTEON 10, and PRESTERA switches for base stations of G5 networks. The company already started to supply initial components to its customers. In August 2020 Marvel announced the expansion of its cooperation with Taiwanese company TSMC. As part of this cooperation, both companies announced that the new OCTEON processors will be built in TSMC’s 5nm process.
Both the communication processor and the switch, originally developed in Israel, are the first to be manufactured by Marvell using 5nm technology. VLSI vice president of engineering, in charge of Marvell’s switches, told Techtime that the moving to the new production technology required special adjustments: “It required us to develop new IP modules and to perform architectural modifications which utilize the 5nm advantages”.
The Israeli R&D center involves in developing chips to the connectivity and processors field, which is considered to be significant economic growth engine foe Marvell. The center employs several hundreds of employees, most of them in Petach-Tikva & Yoqne’am centers, and the rest of them in smaller centers throughout India, China and the USA. According to Heruti, the transition to the new technology was crucial, as the new switches – which are based on PRESTERA architecture – are going to handle the connectivity between the antenna and the base unit (Fronthaul) within 5G networks and between the processors of the system.
Heruti: “These networks have a 100-fold increase in the communication transfer rate comparing to G4 networks – from 100Mbps to 10Gbps. They also have to struggle very short delay intervals, as the time required to transmit the information from one end of the network to the other had shortened from 20ms to 1ms. It has to make sure the switch provides deterministic performance, with zero peaks, as the level of communication continuity dictates service level”.
The OCTEON chip is of System-on-Chip (SoC) type, composed of a bundle of 8-36 CPU processors (ARM Neoverse N2 model), encryption accelerators, artificial intelligence accelerators, data processing accelerators and circuits that provide support for various protocols. The DPU have to manage the communication against thousands of resources, handle new communication protocols with widespread use of frequency multiplication, while allowing for future network expansion. “We currently use these switches in both cloud-farms and in communication infrastructure, while in the cloud applications it is intended to provide support in the main server processor and perform load shifting from the CPU, in the communication area it is served as the system’s main processor.