[In the figure, taken from the study, a three-dimensional structure of transistor layers — oxide, organic, and hybrid — is shown stacked one atop another to form a single complementary circuit. The diagram illustrates how combining different materials enables the construction of a vertical chip in which each layer serves a unique function within the circuit.]
In a breakthrough that could redefine the limits of chip design, researchers at King Abdullah University of Science and Technology (KAUST) have built a “multi-story” 3D chip consisting of 41 active layers — not by further shrinking transistors, but by building upward.
Each layer contains transistors, wiring, and insulators, all connected into a single, functioning circuit. It marks the first demonstration of such a tall electronic structure operating as one computational system.
This achievement presents a practical alternative to Moore’s Law, the rule of thumb that has guided semiconductor progress for more than half a century. After decades of scaling transistors down to just a few nanometers, engineers have hit physical and economic limits — including heat dissipation, manufacturing cost, and precision barriers. The KAUST team proposes a different route: rather than making transistors smaller, simply add a new dimension — height.
A Revolution in Construction, Not Packaging
To grasp the magnitude of the achievement, it’s essential to distinguish KAUST’s approach from commercial 3D Packaging technologies used by Intel, AMD, and TSMC.
In 3D Packaging, completed chips — such as a CPU, memory die, or power-management chip — are stacked and connected using TSV (Through-Silicon Vias) or hybrid bonding. These methods mechanically combine pre-fabricated components, each made separately in a conventional process.
At KAUST, however, no pre-made chips were stacked. The researchers built the entire chip from the bottom up, with each layer fabricated in sequence at low temperatures to avoid damaging the ones beneath it. Every “floor” was made from a different material — including IGZO (Indium Gallium Zinc Oxide) and MoS₂ (Molybdenum Disulfide) — ultra-thin semiconductors with outstanding electronic properties.
This combination enabled both n-type and p-type transistors to coexist in the same structure, allowing the creation of full complementary (CMOS) circuits without using silicon at all.
Massive Density, Minimal Power
The prototype integrates tens of thousands of transistors within a single vertical stack. This architecture shortens communication distances between components, dramatically reducing power consumption and improving switching speed.
Each layer is optimized for its specific role — processing, memory, or signal control — enabling a structural efficiency that flat, two-dimensional chips simply cannot achieve.
Despite initial concerns, thermal management remained stable. The researchers used insulating materials with high thermal conductivity and a geometry that disperses heat evenly across the stack. The result: a prototype operating at low and stable voltages — an impressive feat for a structure dozens of nanometers tall.
A Chip for Both Body and Brain
Professor Xiaohang Li, who led the research, emphasized that the project’s goal is not merely to break density records, but to pioneer a new paradigm for truly three-dimensional computing.
“Our approach,” he said, “is especially suited to flexible electronics, wearable devices, and large-area sensor systems that require both surface area and energy efficiency. It could also serve as a foundation for neuromorphic computing — mimicking the brain’s natural 3D architecture.”
The team views the ability to combine different materials in each layer as a critical advantage. Some layers can handle logic, others memory, all linked directly without long metal interconnects. The result is “a single, multifunctional chip” in which information moves seamlessly between logic and memory — a potential solution to the von Neumann bottleneck, where the physical separation of processor and memory limits data-transfer speed.
Beyond Moore’s Law
The technology remains at a laboratory stage, but it signals a clear direction: Moore’s Law doesn’t have to be “saved” by further miniaturization — it can be extended by expanding into the third dimension.
In this sense, KAUST’s work echoes Intel’s introduction of the FinFET in the early 2000s, a geometric innovation that prolonged the silicon era. If the team can prove scalability to mass production, the semiconductor industry could gain a new roadmap — one no longer defined by Moore’s Law, but by a new principle entirely: the law of height.
Founded in 2009, KAUST has become a global research powerhouse in science and technology. The 3D-chip project was led by Professor Xiaohang Li, a specialist in wide-bandgap materials and advanced transistor design, whose lab spearheads the university’s pioneering semiconductor research.