Weebit Nano (ASX:WBT) has completed the design and verification of embedded ReRAM module, and taped-out a test-chip for testing and qualification. “The test chip allows Weebit to demonstrate a fully functional ReRAM memory product, “that can be readily integrated into System-on-Chip,” said Weebit’s CEO, Coby Hanoch.
The ReRAM (Resistive Random Access Memory) module comprises a full sub-system in which the module is embedded. It also includes a RISC-V microcontroller (MCU), system interfaces, Static Random-Access Memory (SRAM) and peripherals. It was designed for ST 130nm process and consists of a 128Kb ReRAM array, control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC).
Weebit expects to recieve the first silicon towards the end of 2021, and to demonstrate the module in the first quarter of 2022. Qualifications are expected to be completed by mid-2022. ReRAM is an emerging technology that combines the advantages of both DRAM and Flash: It is a non-volatile, extremely fast, low-power and can endure significantly higher number Program/Erase cycles than Flash memory.
Weebit’s ReRAM cell consists of 2 metal layers with a Silicon Oxide (SiOx) layer between them. In an initial, one-time, forming step, positive voltage is applied on the cell to form a conductive filament, and entering a Low Resistive State. After that – applying positive and negative voltages can cause the cell to move from one state to the other. For now the company is focused on the embedded applications market, delivering solutions to semiconductor customers and fabs who embed its IP into their SoCs. The long tem goal is into the broad market for discrete memory devices.