Synopsys Announced a new simulator for converged ICs

Synopsys announced the PrimeSim Continuum solution, a unified workflow for circuit simulation technologies to accelerate the creation of hyper-convergent designs. PrimeSim Continuum is built on SPICE and FastSPICE architectures – a proven GPU acceleration technology providing runtime improvements and signoff accuracy. “PrimeSim Continuum represents a revolutionary breakthrough in circuit simulation,” said Sassine Ghazi, Chief Operating Officer at Synopsys.

Today’s hyper-convergent SoCs consist of larger and faster embedded memories, analog front-end devices and complex I/O circuits that communicate at 100Gb+ data rates with the DRAM stack connected on the same piece of silicon in a system-in-package design. This results in more simulations with longer runtimes at higher accuracy. PrimeSim Continuum addresses this complexity with a unified workflow of sign-off quality simulation engines tuned for analog, mixed-signal, RF, custom digital memory designs. Synopsys said it optimizes the use of CPU and GPU resources and improve time-to-results and cost of results.

“As modern compute workloads evolve, the size and complexity of analog designs have moved beyond the capacity of traditional circuit simulators,” said Edward Lee, vice president of Mixed Signal Design at NVIDIA. “Using NVIDIA GPUs enables PrimeSim SPICE to accelerate circuit simulation, notably minimizing signoff time of analog blocks from days to hours.” The Synopsys PrimeSim Continuum solution is now available. For more information: PrimeSim Continuum.

Synopsys Delivers New ZeBu Empower Emulation System for Hardware-Software Power Verification

Synopsys, Inc. (Nasdaq: SNPS) announced the immediate availability of ZeBu® Empower emulation system, delivering breakthrough technology for fast hardware-software power verification of multi-billion gate SoC designs. The performance of ZeBu Empower enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. With ZeBu Empower, software and hardware designers can utilize the power profiles to identify substantial power improvement opportunities for dynamic and leakage power much earlier. The ZeBu Empower emulation system also feeds forward power-critical blocks and time windows into Synopsys’ PrimePower engine to accelerate RTL power analysis and gate-level power sign-off.

Traditionally, power analysis with realistic software workloads is performed post-silicon, introducing a high amount of risk to miss critical high-power situations, which exposes companies to significant cost and product adoption risk. By taking advantage of high-speed emulation in ZeBu Empower, design teams can perform verification earlier in the design cycle, dramatically reducing risks of power bugs and missed SoC power goals.

“The industry’s need to shift-left software development from post-silicon to pre-silicon has driven tremendous adoption of our ZeBu Server over the last five years,” said Manoj Gandhi, general manager of the Verification Group at Synopsys. “Our breakthrough technology in ZeBu Empower addressees our customers’ need for hardware-software power verification enabling them to develop a new generation of power optimized SoCs.”

“As high-performance designs and workloads continue to grow in complexity, achieving leadership performance within a thermal envelope is important for our products,” said Alex Starr, Corporate Fellow, Technology and Engineering at AMD. “Solutions that allow us to efficiently profile power consumption across real workloads in a pre-silicon environment help us achieve our product goals. Synopsys’ ZeBu Empower, operating in collaboration with servers using 2nd Gen AMD EPYCTM processors, has enabled us to perform pre-silicon power analysis more efficiently in a quicker time.”

The Synopsys ZeBu Empower emulation system for hardware-software power verification solution is available now.

Synopsys offers a comprehensive solution for low power design and verification, including RTL-based early power exploration to the industry’s golden power signoff; from early static verification to emulation-based hardware-software power verification. Synopsys’ innovative low power solutions are deployed across some of the most demanding designs, globally.

Synopsys Acquired Light Tec

Synopsys has acquired Light Tec, a French-based provider of optical scattering measurements solutions. The acquisition allows Synopsys to combine its optical design software tools with Light Tec’s solutions expands customer access to precision light scattering data for materials and media used in optical systems.

The terms of the deal were not being disclosed. Light scattering data provides designers with accurate information to predict how light reflects and transmits in an optical system. It is used to obtain high-precision simulation results for a wide range of applications such as optical sensors, displays, semiconductors, and luminaires. Light scattering data is also important for demonstrating optical product spectral behavior in photorealistic renderings.

“Light Tec’s optical measurement capabilities provide our customers with robust new tools for high-accuracy optical product simulations and visualizations,” said Dr. Howard Ko, general manager of Synopsys’ Silicon Engineering Group. Synopsys is in a process of expanding its presence in the optics market design tools. In September, 2020, it launched the OptoCompiler platform for photonic integrated circuit (PIC) design.

Unified Electronics and Photonics Design Tool

OptoCompiler is one of the industry’s first unified electronic and photonic design platform that combines industry-proven electronic design tools with optical design tools. Widespread implementation of PICs has, until now, been impeded because many design tools were intended for electronics rather than photonics. As a result, photonic design has largely been the domain of experts who could build their own tools or repurpose a disparate toolset.

OptoCompiler provides support for electronic-photonic co-design to ensure scalable design processes. “With OptoCompiler, we aim to make photonic design as productive as digital,” said Tom Walker, group director of Synopsys’ Photonic Solutions. Synopsys started this move in 2012, when it acquired RSoft Design Group, a provider of photonics design and simulation software headquartered in New York.

Arbe Robotics Selected EV62 Processor from Synopsys for its Imaging Radar

The next Radar SoC for vehicles will be based on a suite of solutions from Synopsys’ DesignWare IP. Last month the Israeli startup company Arbe Robotics announced it has raised $10 million in a round led by French VC 360 Capital Partners, The company said it will use the proceeds to enhance its imaging technology and to expand its operations in the US and China. With this round, the total funding into the firm stands at $23 million.

Lately the company revealed more data on its future radar device. Arbe Robotics’ imaging radar is designed for advanced driver assistance systems (ADAS) and autonomous vehicles. The imaging radar can sense the environment at a wide 100-degree field of view in high-resolution at all weather conditions, including fog, heavy rain, pitch darkness, and air pollution. It is able to create a detailed image of the road at a range of more than 300 meters (1,000 feet) and capture the size, location, and velocity data of objects surrounding the vehicle in accuracy of 10-30 cm.

Synopsys said that Arbe Robotics selected its DesignWare ARC EM Safety IslandEV6x Embedded Vision Processor with Safety Enhancement PackageEthernet Quality-of-Service Controller IP, and STAR Memory and STAR Hierarchical System. “Radar chips for autonomous vehicles require both a high level of processing capabilities and integrated safety features, to detect and prevent system failures,” said Kobi Marenko CEO at Arbe Robotics.

Arbe Robotics selected the ARC EM6SI Safety Island because of its integrated self-checking safety monitor, error correcting code (ECC), and programmable watchdog timer. The EV62 Embedded Vision Processor with SEP provides a dual core 512-bit wide SIMD vector DSP, and required functional safety capabilities without sacrificing performance. Both processors feature lockstep capabilities for detection of system failures and runtime faults.